In recent years, attention has been paid to a resistive memory as a candidate for a successor to a flash memory. It is assumed that resistive memory devices include not only a resistive memory (ReRAM: Resistive RAM) in a narrow sense, in which a transition metal oxide is used as a recording layer and a resistance value state thereof is stored in a nonvolatile manner, but also a phase-change memory (PCRAM: Phase Change RAM) in which a chalcogenide or the like is used as a recording layer and resistance value information of its crystalline state (conductor) and noncrystalline state (insulator) is utilized.
It is known that a variable resistance element of the resistive memory has two operation modes. One of the two operation modes is called “bipolar mode” in which a high resistance state and a low resistance state are set by changing the polarity of application voltage. The other is called “unipolar mode” in which a high resistance state and a low resistance state can be set by controlling a voltage value and a voltage application time.
In order to realize a high-density memory cell array, the unipolar type is preferable. In the case of the unipolar type, a cell array can be constructed without using a transistor, by overlaying a variable resistance element and a rectification element, such as a diode, at an intersection between a bit line and a word line. Furthermore, by stacking such memory cell arrays in a three-dimensional fashion, a large capacity can be realized without increasing the cell array area.
In order to increase the integration density of memory cell arrays and to realize a low-cost memory chip, it is necessary to decrease the number of divisions of the memory cell array and to stack largest possible cell arrays as many as possible in the vertical direction. In this case, however, the distance between a peripheral circuit and the memory cell array increases, and such a case arises that a large parasitic capacitance occurs in the wiring between the bit line and the peripheral circuit. Such a large parasitic capacitance may become a cause of an erroneous write operation or an erroneous erase operation in the memory cell.